The invention relates to an integrated circuit topography for a high speed operational amplifier.
By way of background regarding topography of integrated circuit chips, the size of an integrated circuit chip is an important factor in the ultimate cost to the final user. Another important factor is the engineering and design cost. Increasing the number of chips which are included on each wafer reduces the manufacturing cost per chip because the cost of each wafer is approximately constant. The chip size becomes an increasingly dominant factor in the ultimate product cost as the manufacturing volume increases. On each chip there are many conductive lines, some composed of aluminum or other metalization, on one or more insulative layers. Other conductors are composed of diffused regions within the silicon material of the chip. For some processes, polycrystalline silicon layers form some of the conductors. The various conductors interconnect the various electrodes of various circuit elements such as lateral PNP transistors, vertical NPN and PNP transistors, diffused resistors, thin film resistors, and metal capacitors all of which are formed using conventional bipolar manufacturing wafer fabrication processes. Specified line widths and spacings between the respective conductors and circuits element parts on each insulative layer must be maintained to avoid short circuits therebetween and to limit various parasitic effects. There often are variations in the manufacturing process parameters due to machine calibration errors and minute particulates that are invariably present in a semiconductor processing facility, and the presence of such variations dictates that the specified widths and spacings be adhered to. Furthermore, the conductor lengths, and hence their associated capacitances and resistances, must be minimized not only to reduce chip size, but also to achieve maximum circuit operating speed.
Those skilled in the art of integrated circuit chip design know that there are a number of design tradeoffs, including the desirability of minimizing chip size, obtaining suitable chip aspect ratios, increasing circuit operating speed, reducing power consumption, and avoiding various undesirable thermal effects. Such thermal effects can be due to localized DC and transient power dissipation by various transistors on the chip and also due to the sensitivity of other transistors on the chip to such thermal effects. More specifically, some of the numerous design constraints faced by the chip designer include specifications for minimum widths and spacings of diffused regions in the silicon, the minimum sizes required for contact openings between the insulating field oxide, the spacings required between edges of contact openings to edges of diffused regions, minimum widths and spacings of metal conductors, the availability or nonavailability of multiple metalization layers and conductive vias interconnecting the various layers, and the constraint that conductors on the same "layer" of the chip cannot cross one another. The large amount of capacitance associated with diffused regions must be carefully considered by the circuit designer and the chip designer in arriving at an optimum chip topography. The practically infinite number of possibilities for routing the various conductors and placement of the various transistors, resistors and capacitors on an integrated circuit taxes the skill and ingenuity of even the most resourceful chip designers and circuit designers and is beyond the capability of the most sophisticated computer layout programs yet available. Other constraints faced by the chip designer and the circuit designer involve the need to minimize cross-coupling and parasitic effects which occur between various conductive lines and conductive regions. Such effects may degrade voltages on various conductors, leading to inoperative circuitry, reduced performance or low reliability operation under certain operating conditions.
Often, the technical and commercial success of an integrated circuit chip may hinge on the ability of the "chip designer" or "layout designer" to achieve an optimum circuit topography, and often that topography is only obtained as a result of a great deal of interaction between the circuit designers and the layout designers and careful balancing of the above tradeoffs.
Thus, those skilled in the art know that a very high level of creative interaction between the circuit designer and the chip designer or layout draftsman may be required to achieve a chip topography or layout that enables the integrated circuit to have acceptably high operating speed, acceptably low power dissipation, acceptable immunity from differential or transient thermal conditions in the chip, and yet is sufficiently small in size to be economically advantageous.
By way of background regarding good thermal design of an integrated circuit, thermal design of a bipolar integrated circuit chip requires careful consideration of the locations of transistors that when operated produce significant "differential heating" of localized regions of the chip. Good thermal design of the chip also requires careful consideration of the locations of transistors the operation of which are significantly affected by such differential heating. Good thermal design of a chip generally involves determination of the location of a "thermal centroid" of a transistor or group of transistors which produce significant differential heating effects, and then locating such transistor or group of transistors so that its thermal centroid lies on a preestablished "thermal centerline" of the chip. Similarly, thermal centroids of heat sensitive transistors, herein called "heat receptors", or groups of such heat receptor transistors should be located on the thermal centerline of the chip, or should be located as far away as possible from the source of significant differential heating effects. Failure to provide good thermal design of a chip may result in reliability problems, offset problems, linearity problems, and/or otherwise unacceptable circuit performance as a result of unbalanced differential heating of transistors which are in the main signal path or in critical bias circuits.
These considerations, in addition to the requirements mentioned above, add considerably to the challenge of providing an overall chip topography which is optimum from the various viewpoints of reliable, high speed, low power operation. In general, transistors which carry low level signals should be located symmetrically with respect to the thermal centerline of the chip so that they are equally affected by transient thermal effects produced by other transistors on the chip, which also should be located symmetrically with respect to the thermal centerline. Generally, a transistor that has a substantial collector voltage swing has a possibility of being a substantial differential heat generator, and its location must be carefully considered with respect to any transistors in the signal path which might be affected by transient temperature changes of its emitter-base junction.
For these reasons, it is typical in operational amplifier integrated chip layouts to prevent some of the possible differential thermal effects from increasing the amplifier input offset, affecting the open loop gain, and affecting the amplifier linearity by establishing a thermal centerline of the chip and locating differential heat generating transistors on the thermal centerline. It also is conventional to split "heat receptor" transistors into two equal, parallel-connected parts and place such parts symmetrically on opposite sides of the thermal centerline.
By way of background regarding high speed operational amplifiers, they are sensitive to high frequency noise disturbance because the internal parasitics, which would be large enough in slower amplifiers to attenuate the noise, are very much reduced and consequently allow the noise signals to pass. These amplifiers are also sensitive to high frequency noise disturbance because the high bandwidth of the active elements amplifies the noise signals.
The applications of high speed amplifiers expose them to high frequency noise disturbance coupled by stray circuit parasitics into power supply conductors and other circuit connections. The amplifiers also generate high frequency noise disturbance on internal connections as they respond to large signal high frequency input signals.
FIG. 1 is a simplified schematic diagram of an OPA646 wide bandwidth operational amplifier marketed by Burr-Brown Corporation of Tucson, Arizona which is believed to be the closest prior art to the present invention. The operational amplifier 1 of FIG. 1 includes a differential input stage 3 including NPN input transistors 4 and 5. The differential input signal is applied between the bases of input transistors 4 and 5. The emitters of input transistors 4 and 5 are connected to an NPN current mirror output transistor 6, the emitter of which is coupled through a low value resistor 7 to the negative power supply voltage -V.sub.EE. -V.sub.EE typically is -5 volts. The collectors of input transistors 4 and 5 are coupled by load resistors 8 and 9, respectively, to the positive supply voltage +V.sub.CC, which typically is +5 volts. The collectors of input transistors 4 and 5 also are coupled to the emitters of PNP "folded cascode" transistors 17 and 18 included in gain stage 19. The output 25 of gain stage 19 is coupled to the input of a diamond follower unity gain buffer 20 which produces an output V.sub.OUT on conductor 40.
The bases of PNP "folded cascode" transistors 17 and 18 are connected by conductor 33 to the base of PNP current mirror control transistor 15. The emitter of PNP current mirror control transistor 15 is connected through a low value resistor 28 to the positive power supply voltage +V.sub.CC. The base of PNP current mirror control transistor 15 also is connected to the emitter of a PNP "darlington" transistor 16, the base of which is connected by conductor 21 to the collector of PNP transistor 15 and to one terminal of a current source circuit 10. (Current source 10 includes a resistor schematically drawn to represent the impedance thereof.) The "darlington" transistor 16 is needed to reduce error in the PNP current source output transistor collector currents due to the low beta of PNP transistors manufactured using typical "high speed" bipolar manufacturing processes. Conductor 21 also is connected to one terminal of a 1.5 picofarad compensation capacitor 24, the other terminal of which is connected to +V.sub.CC. Conductor 33 also is connected to the base of a PNP current mirror output transistor 29 to establish operating current for diamond follower 20.
The collectors of PNP folded cascode transistors 17 and 18 are connected to other circuitry in gain stage circuit 19 which produces an output signal on conductor 25 that is applied to the input of diamond follower unity gain buffer 20.
An NPN current mirror control transistor 11 has its collector and base connected by conductor 22 to a second terminal of current source 10, and also to one terminal of a second compensation capacitor 23 having its other terminal connected to V.sub.CC. Conductor 22 also is connected to the base of NPN current mirror output transistor 6 and to the base of an NPN current mirror output transistor 13 which establishes operating current for diamond follower 20. A low value resistor 12 is connected between the emitter of NPN current source control transistor 11 and -V.sub.EE. The emitters of transistors 6 and 13 are also connected by low value resistors to -V.sub.EE.
The base of transistor 18 is connected to the base of PNP transistor 29 which biases diamond follower 20. The emitter of transistor 29 is coupled by a resistor to +V.sub.CC.
Those skilled in the art know that transient imbalances between the constant currents produced in the collectors of the NPN current mirror output transistors 6 and 13 and the collectors of PNP current mirror output transistors 17, 18 and 29 can produce undesirable transient signal operation of the operational amplifier 1 that results in "ringing" of the output voltage V.sub.OUT produced on conductor 40 when it rapidly swings or "slews" toward the +V.sub.CC level or the -V.sub.EE level. Those skilled in the art also realize that PNP "darlington" transistor 16 and PNP current mirror control transistor 15 form a loop which may oscillate at high frequencies. Therefore, compensation capacitor 24 needs to have a sufficiently high value to prevent such oscillating. In the OPA646 operational amplifier of FIG. 1, the value of the capacitance of compensation capacitor 24 is 1.5 picofarads.
Also, noise or "glitches" on the +V.sub.CC power supply conductor can cause imbalances in the voltages on conductors 21 and 22 by coupling unequal amounts of noise energy thereto, resulting in imbalances between the currents in the collectors of the various PNP current mirror output transistors and the currents in the collectors of the various NPN current mirror output transistors, especially if compensation capacitors 23 and 24 are mismatched. Those skilled in the art know that provision of compensation capacitors such as 23 and 24 on an integrated circuit requires much more chip area than is desirable, thereby increasing the size of the chip, increasing its cost, and sometimes decreasing its speed and manufacturing yield.